Abstract:
This master thesis serve as a starting point for developing a digital signal processor with scalable structure. The digital signal processor is a common and important part of digital processing. Scalable struture is in this case adding and removing parts of the memory and/or the instruction set, and to make the data wordlength variable. The development is simplified by modeling it on an existing processor. The result of this master thesis is an instruction simulator written in C language. The simulator will be a model for development of the hardware.
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