Power consumption of Reed-Solomon decoder algorithms

Abstract:


The Core Unit ASIC Technology & System on Silicon at Ericsson Micro Wave Systems has a project on STM-1 / SDH communication over a microwave link called Mini Link. They want to have a power effective Reed-Solomon encoder to correct bit errors. In this master's thesis three different algorithms for Reed-Solomon codes are implemented in hardware using VHDL and then compared by power consumption. The Reed-Solomon code implemented is an RS (255,239) that handles errors but not erasures.The different algorithms used are Berlekamp-Massey, Gröbner basis by Fitzpatrick and Welch-Berlekamp. They are implemented in VHDL and first compared by the size after being synthesized, then compared by power dissipation estimated for non, four and eight errors per block with Watt Watcher from Sequence. The Berlekamp-Masey had the lowest power dissipation for all error rates and the smallest size. However, no real winner could be selected among the algorithms since the differences in size and power dissipation where so small.

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