Low power ASIC design of a wideband CDMA combiner

Abstract:

This thesis is a study of low power ASIC design of a WCDMA combiner. Thefocus is on low power design flow and different techniques used for low powerASIC's and how this can be used designing a WCDMA combiner. Differentarchitectures and logic optimizations are evaluated by estimating the powerconsumption.In a mobile station the power consumption is a very important issue. With lowpower the size of the battery can be reduced or the usage time can beincreased. Low power should be considered throughout the whole design cycleand not at a single location. Therefore, it is important to look at what canbe done to reduce the power consumption and to avoid increasing power usage.Architecture selection and voltage scaling was explored to reduce powerconsumption in the thesis. This was done by writing VHDL for the differentarchitectures and following the design flow for low power design. The powerconsumption was estimated and optimized with EDA tools. During the evaluationof the architectures, it was found that the resource-shared architectures hadsignificant higher power consumption than the non-shared structures. Thisresulted in the selection of a non-shared architecture.

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