A Behavioral Model of a DSP Processor with Scalable Structure

Abstract:

 

In mobile digital devices, low power consumption is an important matter to reduce the need for a heavy and big battery. One way of reducing the power consumption is to construct the hardware so that the performance is optimal for the application. The demand of performance is dependent of the tasks that the device will be performing. This is where scalable structure of the hardware is an idea to solve the problem.
This master thesis serve as a starting point for developing a digital signal processor with scalable structure. The digital signal processor is a common and important part of digital processing. Scalable struture is in this case adding and removing parts of the memory and/or the instruction set, and to make the data wordlength variable. The development is simplified by modeling it on an existing processor. The result of this master thesis is an instruction simulator written in C language. The simulator will be a model for development of the hardware.
 

Behavioral Model of an Instruction Decoder of Motorola DSP56000 Processor

Abstract:

 

This thesis is a part of an effort to make a scalable behavioral model of the Central Processing Unit and instruction set compatible with the DSP56000 Processor. The goal of this design is to reduce the critical path, silicon area, as well as power consumption of the instruction decoder.
The instruction decoder consists of three different types of operations instruction fetching, decoding and execution. By using these three steps an efficient model has to be designed to get the shortest critical path, less silicon area, and low power consumption.

Design of a Finite-Impulse Response filter generator

Abstract:

 

In this thesis a FIR filter generator has been designed. The program generates FIR filters in the form of VHDL-files. Four different filter structures have been implemented in the generator, Direct Form (DF), Differential Coefficients Method (DCM), polyphase filters and (2-by-2) filters.
The focus of the thesis was to implement filter structures that create FIR filters with as low power consumption and area as possible.
The generaterator has been implemented i C++. The C++ program creates text-files with VHDL-code. The user must then compile and synthesize the VHDL-files. The program uses an text-file with the filter coefficients as input.

System Design of RF Receiver and Digital Implementation of control logic

Abstract:

 

This report is the outcome of a thesis work done at Linköpings University, campus Norrköping. The thesis work was part of the development of a RF transceiver chip for implantable medical applications. The development was done in cooperation with Zarlink Semiconductor AB, located in Järfälla, Stockholm.
The transceiver is divided into three main blocks, which are the wakeup block, the MAC block and the RF block. The wakeup block is always operating and is awaiting a wakeup request in the 2,45GHz ISM-band. The RF-block is operating in the 400MHz ISM-band and is powered up after wakeup The MAC is the controller of the whole chip. All three blocks in the transceiver structure should be integrated on the same chip, using TSMC 0,18µm process design kit for CMOS (Mixed Signal /RF).
The purpose of the thesis work was to develop the wakeup circuit for the transceiver. The main purpose was to develop the digital control logic in the circuitry, using RTL-coding (mainly VHDL) but the thesis work also included a system analysis of the whole wakeup block, including the front-end, for getting a better overview and understanding of the project.
A complete data packet or protocol for the wakeup message on 2,45GHz, is defined in the report and is one of the results of the project. The packet was developed continuously during progress in the project. Once the data packet was defined the incoming RF stage could be investigated. The final proposal to a complete system design for the wakeup block in the RF transceiver is also one of the outcomes of the project. The front-end consists mainly of a LNA, a simple detector and a special decoder. Since the total power consumption on the wakeup block was set to 200nA, this had to be taken under consideration continuously. There was an intention not to have an internal clock signal or oscillator available in the digital part (for keeping the power consumption down). The solution to this was a self-clocking method used on the incoming RF signal. A special decoder distinguishes the incoming RF signal concerning the burst lengths in time. The decoder consists of a RC net that is uploaded and then has an output of 1, if the burst length is long enough and vice versa.
When it was decided to use a LNA in the front-end, it was found that it could not be active continuously, because of the requirements on low power consumption. The solution to this was to use a strobe signal for the complete front-end, which activates it. This strobe signal was extracted in the digital logic. The strobe signal has a specific duty cycle, depending on the time factors in the detector and in the decoder in the front-end. The total strobing time is in the implemented solution 250µs every 0,5s.
The digital implementation of the control logic in the wakeupblock was made in VHDL (source code) and Verilog (testbenches). The source code was synthesized against the component library for the process 0,18µm from TSMC, which is a mixed/signal and RF process. The netlist from the synthesizing was stored as a Verilog file and simulated together with the testbenches using the simulator Verilog-XL. The results from the simulations were examined and reviewed in the program Simvison from Cadence. The result was then verified during a pre-layout review together with colleagues at Zarlink Semiconductor AB. During the implementation phase a Design report was written continuously and then used for the pre-layout review. Extracts (source code and testbench) from this document can be found as appendixes to the report.

Design and Implementation of Sampling Rate Converters

Abstract:

 

In different applications, in digital domain, it is necessary to change the sampling rate by an arbitrary number. For example Software Radio which should handle different conversion factors and standards.
This work focuses on the problem of designing and implement sampling rate converters for conversions between arbitrary sampling rates.
The report presents an overview of different converter techniques as well as considers a suitable scheme with low implementation cost. The creating VHDL generator of Farrow-based structure to speed up the design process is the main task of this work. The suitable design technique which is the most important thing in any design work is presented in the report as well.
The scheme which is considered to be suitable is created by VHDL generator and tested in MATLAB. The source code is attached to the report. And some results from tests of the implemented scheme.