Development and Implementation of a Low Power Wireless Senssor network

Abstract:

 

The wish to measure different environmental parameters, in for example office buildings, is getting more and more important in today’s society. Since the sensors should be easily deployed they need to be battery powered and communicate wireless. Furthermore the radio range must be extended because of the limited range on the free frequencies. This is where wireless sensor networks come in and extend the range by relaying the data through other nodes in the network, thereby extending the total range of the network.
The purpose of this thesis work is to develop a protocol for such a wireless sensor network, capable of delivering and relaying sensor data through the nodes of the network.
The protocol has been implemented in hardware also designed in this thesis. Tests of the network have been performed and the results have shown that the network works very well and fulfills all of the requirements. Furthermore the power consumption is only 15% of the required value. This thesis has produced a very good platform to use as a base for further development of a commercial product.

Efficient ASIC implementation of a WCDMA Rake Receiver

Abstract: 


This thesis is a study of a efficient ASIC implementation of a WCDMA Rake Receiver for the third generation mobile communication (3G) terminals. The focus has been on doing a implementation with small memory footprint and low power consumption.

Functional Self-Test of DSP cores in a SOC

Abstract:

 

The rapid progress made in integrating enormous numbers of transistors on a single chip is making it possible for hardware designers to implement more complex hardware architectures in their designs. Nowadays digital telecommunication systems are implementing several forms of SOC (System-On-Chip) structures. These SOCs usually contain a microprocessor, several DSP cores (Digital-Signal-Processors), other hardware blocks, on-chip memories and peripherals.
As new IC process technologies are deployed, with decreasing geometrical dimensions, the probabilities of hardware faults to occur during operation are increasing. Testing SOCs is becoming a very complex issue due to the increasing complexity of the design and the increasing need of a test mechanism that is able to achieve acceptable fault coverage in a short test application time with low power consumption without the use of external logic testers.
As a part of the overall test strategy for a SOC, functional self-testing of a DSP core is considered in this project to be applied in the field. This test is used to verify whether fault indications in systems are caused by permanent hardware faults in the DSP. If so, the DSP where the fault is located needs to be taken out of operation, and the board it sits on will be later replaced. If not, the operational state can be restored, and the system will become fully functional again.
The main purpose of this project is to develop a functional self-test of a DSP core, and to evaluate the characteristics of the test. This project also involves proposing a scheme on how to apply a functional test on a DSP core in an embedded environment, and how to retrieve results from the test. The test program shall run at system speed.
To develop and measure the quality of the test program, two different coverage metrics were used. The first is the code coverage metric achieved by simulating the test program on the RTL representation of the DSP. The second metric used was the fault coverage achieved. The fault coverage of the test was calculated using a commercial Fault Simulator working on a gate-level representation of the DSP. The results achieved in this report show that this proposed approach can achieve acceptable levels of fault coverage in short execution time without the need for external testers which makes it possible to perform the self-test in the field. This approach has the unique property of not requiring any hardware modifications in the DSP design, and the ability of testing several DSPs in parallel.

Improved implementation of a 1K FFT with low power consumption

Abstract:

 

In this master thesis, a behavioral VHDL model of a 1k Fast Fourier Transform (FFT) algorithm has been improved, first to make it synthesizable and second to obtain a low power consumption. The purpose of the thesis has not been to focus on the FFT algorithm itself or the theory behind it. Instead the aim has been to document and motivate the necessary modifications, to reach the stated requirements, and to discuss the results. The thesis is divided into sections so that the design flow closely can be followed from the initial FFT, down to the final architecture. The two major design steps covered are synthesis and power simulation. The synthesis process has been the most time consuming part of the thesis.
The synthesis tool Cadence Ambit PKS was used. Throughout the synthesis, the modifications and solutions will be discussed and comparisons are continuously made between the different solutions and the initial FFT. The best solution will then be the starting point in the next design step, which is simulation of the design with respect to power consumption. This is done by using a simulation tool from Synopsys called NanoSim. Also here, every solution is tested and compared to each other, followed by a concluding discussion. The technology used to implement the design is a 0.35um CMOS process.

Low power ASIC design of a wideband CDMA combiner

Abstract:

This thesis is a study of low power ASIC design of a WCDMA combiner. Thefocus is on low power design flow and different techniques used for low powerASIC's and how this can be used designing a WCDMA combiner. Differentarchitectures and logic optimizations are evaluated by estimating the powerconsumption.In a mobile station the power consumption is a very important issue. With lowpower the size of the battery can be reduced or the usage time can beincreased. Low power should be considered throughout the whole design cycleand not at a single location. Therefore, it is important to look at what canbe done to reduce the power consumption and to avoid increasing power usage.Architecture selection and voltage scaling was explored to reduce powerconsumption in the thesis. This was done by writing VHDL for the differentarchitectures and following the design flow for low power design. The powerconsumption was estimated and optimized with EDA tools. During the evaluationof the architectures, it was found that the resource-shared architectures hadsignificant higher power consumption than the non-shared structures. Thisresulted in the selection of a non-shared architecture.